Massoud Pedram

Stephen and Etta Varra Professor

Department of EE-Systems

University of Southern California


Previous Projects
Previous Presentations

Current Projects

 

Energy-Efficient, Low-Latency Realization of Neural Networks Through Boolean Logic Minimization

Sponsor:

To cope with computational and storage complexity of deep neural networks, this project focuses on a training method that enables a radically different approach for realization of deep neural networks through Boolean logic minimization. The aforementioned realization completely removes the energy-hungry step of accessing memory for obtaining model parameters, consumes about two orders of magnitude fewer computing resources compared to realizations that use floating-point operations, and has a substantially lower latency.

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Meta-learning

Sponsor:

Meta-learning focuses on learning over the task space rather than instance space by training a general model which is able to quickly adapt to new unseen tasks. The implications of fast adaptation to new unseen tasks can also be effective on the traditional paradigm of neural networks training. Modeling generalization, few-shot learning, and task generation are studied in this project.

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Collaborative Intellignece

Sponsor:

Latency and energy consumption of DNN queries can be significantly improved by splitting the workload between the mobile and cloud. Real-time scheduling of computations between the mobile and cloud and efficient feature communication are studied in this project.

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Advanced Cell Design, Characterization and Re-configurable Circuits for Single Flux Quantum Technology

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

Due to the lack of three-terminal device like MOSFET in CMOS circuits in superconducting electronics, it is difficult to conceive a superconducting FPGA which provides significantly cheaper solutions for various applications. Our work is focused on proposing designing FPGA for superconducting circuits using magnetic Josephson junctions and energy-efficient RSFQ biasing.

 

Placement and Clock Network Synthesis for Single Flux Quantom (SFQ)Logic Circuits

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

In this project new algorithms for placement and clock network synthesis for large scale SFQ circuits a re developed and implemented. The goal is to maximize the circuit performance in terms of maximum clock frequency, considering special characteristics of SFQ technology.

 

Margin and yield calculation for Single Flux Quantum (SFQ) logic cells

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

In this project novel margin calculation methods are introduced for SFQ cels. These methods calculate a set of parameter margins for each logic cell such that if all parameters lie within the boundary of the calculated margins, parametric yield values are near one.

 

Efficient Synthesis and Relization of Single Flux Quantom (SFQ) Logic Circuits

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

This project is about designing suitable computer aided-design (CAD) software tools to support design automation of superconducting single flux quantum circuits. The main focus is on logic and behavioral level synthesis. This includes designing algorithms and implementing them using C/C++ and Python programming languages, and it involves verification of generated circuits through circuit simulations.

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Towards Green Communication: Energy Efficient Solutions for the Next Generation Network

Sponsor:

This project investigates energy efficiency problems in next generation network. Intelligent power m anagement solutions are studied to maximize the utility objective. For example, dynamic switching of base stations, smart scheduling for renewable energy, content caching and cooperative transmission.

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Approximate Computing: A New Approach to Design Energy Efficient Circuits for Error Resilient Applications

Sponsor:

The error resiliency of applications such as media processing has provided designers with a new technique called approximate computing (AC), which abandons exactness of computation in favor of improved efficiency. In functional approximation, which is our focus here, a more simpler function different than the actual design is implemented that can be generated manually by the designer (in the case of approximate arithmetic blocks) or automatically (when an arbitrary function is given). We generated an approximate non-iterative divider which is highly accurate and energy efficient.

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Intelligent Arithmetic Circuit Recognition

Sponsor:

we address the problem of deriving a functional description of a circuit from an unstructured netlist by leveraging deep learning and circuit representations based on convolutional neural networks (CNNs). In doing so, we are motivated by the state-of-the-art performance of machine learning (ML) techniques, based on both convolutional and deep neural networks, for solving challenging problems including classification, pattern recognition, language processing, and decision making in a variety of applications – from business, to social work, medicine, and engineering.

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Verification Techniques for Single Flux Quantom (SFQ) Circuits

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

Objective of this project is to develop the post-synthesis verification techniques for SFQ circuits. As part of this work, we developed a logical equivalence checking (LEC) approach that would check the equivalence of a post-synthesis gate level netlist of a target SFQ circuit against an initial Boolean network representation of the same circuit. In addition to LEC, we work on a semi-formal verification framework for SFQ circuits in the UVM standard. The SFQ logic-focused framework was developed with the best-practice verification methodology of the Universal Verification Methodology (UVM) standard in mind and is easily portable for verifying other SFQ circuit designs.

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SFQ Circuit Design

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

Description: As Moore's law dying for CMOS, novel technology with higher operation rate, better power efficiency and scale-ability is badly demanded for future chips. SFQ is one of the most promising sapling using single quantum flux as the compute unit, holding an advantage of fast speed and low dynamic power. This project is to build a RSFQ cell library, develop novel circuit and system structure for the SFQ logic family and enhance the static power performance for SFQ circuits.

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Minimizing the longest routing wires of large-scale flux circuits

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

Development of a routing tools for single flux quantum (SFQ) circuits. The routing tools aims at finding connection wire paths of all nets of a SFQ circuit while satisfying design rule check. The following is for elaboration: The routing tools are further optimized to identify critical nets with the longest routed wire length and to re-route there nets for a shorter wire length. The routing algorithm for the re-route process is a maze routing algorithm which searches wire paths with the lowest cost of routing individual nets.

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Clocking-Aware Static Timing Analysis for Superconducting Single-Flux-Quantum Circuits

Sponsor: Intelligence Advanced Research Projects Activity (IARPA).

The project is considering popular clocking schemes, like H-tree, concurrent flow, counter flow, data-follow-data, qSTA analyzes a post-routing circuit, check setup and hold timing constraints, and report minimum clock period.

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Accurate gate modeling under variation with neural networks

Sponsor:

Deeply scaled FinFET devices are the optimal choice for low power applications based on their specific characteristics over conventional MOSFET devices. However, these devices are very sensitive to process variation and exhibit non-linear timing and power behavior. Due impact of several number of variation parameters, it is not-practical for the conventional industrial characterization process (e.g. using LUTs) to capture this non-linear behavior. We used neural networks for capturing non-linear timing behavior of deeply-scaled circuits.

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Energy-aware Task Scheduling in Real-Time Systems with Hard Deadline Constraints

Sponsor:

Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) are two major techniques for reducing energy consumption in such embedded systems. Furthermore, MPSoCs are becoming more popular for many real-time applications. One of the challenges of integrating DPM with DVFS and task scheduling of real-time applications on MPSoCs is the modeling of idle intervals on these platforms. In this project, we present a novel approach for modeling idle intervals in MPSoC platforms which leads to a mixed integer linear programming (MILP) formulation integrating DPM, DVFS, and task scheduling of periodic task graphs subject to a hard deadline. We also present a heuristic approach for solving the MILP and compare its results with those obtained from solving the MILP.

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SFQ based ALU design

Sponsor:Intelligence Advanced Research Projects Activity (IARPA).

Description: We plan to exploit the nature of each gate being clocked in SFQ circuits and use this gate level pipelined nature of SFQ logic cells to design a ALU to have better throughput (qBSA). We also, plan to carry forward this research to evaluate the performance of the ALU for Data dependent operations.

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Improving the Energy Efficiency and Lifetime of Coarse-Grained Reconfigurale Architectures

Sponsor:

The error resiliency of applications such as media processing has provided designers with a new technique called approximate computing (AC), which abandons exactness of computation in favor of improved efficiency. In functional approximation, which is our focus here, a more simpler function different than the actual design is implemented that can be generated manually by the designer (in the case of approximate arithmetic blocks) or automatically (when an arbitrary function is given). We generated an approximate non-iterative divider which is highly accurate and energy efficient.

Related work: